Interface Effects of Annealing Temperatures in Al/HfO2/p-Si (MIS) Structures

Abstract

In this study, Al/HfO2/p-Si (MIS) structures were prepared by using the sol-gel method for three different annealing temperatures. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of these structures were investigated by taking into consideration the effect of the interfacial insulator layer and surface states (N-ss) at room temperature. All of the structures showed non-ideal I-V behaviour with ideality factor (n) in the range between 2.35 and 4.42 owing to interfacial insulator layer and surface states. The values of N-ss and barrier height (phi(b)) for three samples were calculated. The values of n and N-ss ascend with increasing the insulator layer thickness (delta) while the values of phi(b) decreases.